The present invention pertains to a process for manufacturing electronic devices comprising high voltage MOS transistors, and an electronic device thus obtained.
Many electronic devices currently present on the market use both NMOS and PMOS high voltage transistors (hereinafter referred to as HV transistors) of the dualgate type (i.e., having the gate region doped with doping ionic species of the same type used for the source and drain regions) and of the drain-extension type. In these manufacturing processes, in order to achieve lengths of the channels of the HV transistors of less than 0.5 xcexcm it is necessary to appropriately increase the doping of the substrate so as to prevent undesired effects, such as punchthrough, i.e., the undesired electrical connection between two regions having different potentials. For this reason, the region designed to house these transistors is enriched with doping ions that may confer on the region the same conductivity type as the substrate, forming a well (or tub) that has a doping level greater than the substrate.
In many devices it is, however, also indispensable to have HV transistors with a low multiplication coefficient (i.e., with a low ratio between the current flowing in the drain region and the current flowing in the substrate) and with a low body effect (i.e., a reduced increase in the threshold voltage of the transistor when the substrate biasing voltage increases), which features require a low doping of the substrate.
A commonly adopted solution to this problem is that of suitably shaping the masks so as to form so-called xe2x80x9cNO-TUBxe2x80x9d HV transistors formed directly in the substrate, instead of in the well or tub.
Since these transistors have a low multiplication coefficient but also a low threshold voltage, they can be used only with appropriate circuit designs to prevent unacceptable parasitic currents. On the other hand, such designs lead to an undesired complication of the circuitry associated to the HV transistors.
The disclosed embodiment of the present invention provides a new process for manufacturing electronic devices comprising HV transistors with a low multiplication coefficient, a low body effect, and a high threshold.
According to the embodiment of the present invention, a process for manufacturing electronic devices comprising HV transistors includes providing a substrate of semiconductor material with a first area having a first conductivity type and a first doping level; forming a first gate region of semiconductor material of the first transistor on the first area of the substrate; and forming in the first area of the substrate, first source and drain regions of a second conductivity type, at the sides of the gate regions, and doping the first gate region with doping species determining the first conductivity type.
In accordance with another aspect of the present invention, the foregoing process includes the step of forming a second high voltage MOS transistor in a second area of the substrate and the step of forming the second high voltage transistor includes: Forming, in the second area of the substrate, a first tub having the first conductivity type and a doping level higher than the first area of the substrate; forming a second gate region having the second conductivity type over the first tub; and forming in the first tub source and drain regions of the second conductivity laterally to the second gate region.
In accordance with yet another aspect of the present invention, the forming of the first source and drain regions and forming of the second source and drain regions is performed simultaneously.